1. Technical Field
The invention disclosed and claimed herein generally relates to a method that uses interrupt coalescing selectively, according to the lengths of respective incoming interrupt messages. More particularly, the invention relates to a balanced method of the above type, wherein an interrupt coalescing technique is applied to long interrupt messages received by a data processing network system, whereas the system is interrupted immediately upon receipt of selected short interrupt messages. Even more particularly, the invention relates to a method of the above type wherein one or more criteria are used to determine whether or not a particular message is sufficiently short and important to warrant immediate interruption of the system processor.
2. Description of Related Art
As is known by those of skill in the art, an interrupt is a signal or message that seeks to redirect operation of a processor in a computer system to a task specified by the interrupt. An interrupt may be sent to the system in the form of packets from a file server, a router, a workstation or the like. However, as is further well known, significant processor overhead is required in processing each interrupt. Accordingly, a number of interrupt coalescing techniques have been developed, to reduce the associated overheads. These interrupt coalescing techniques generally delay delivery of a group of packets until a particular event has occurred, such as receipt of a prespecified total number of packets, receipt of a prespecified number of bytes, or expiration of a prespecified time period. The event could also be receipt of a prespecified number of packets, in combination with expiration of a time period.
A switched Ethernet local area network (LAN) is a typical environment for application of the above interrupt coalescing techniques, although use of these techniques is by no means limited to such environment. An Ethernet LAN is generally provided with an adapter, or network interface card (NIC), that receives incoming packets containing interrupt messages. Interrupt coalescing support is typically implemented in an NIC, either by means of specialized hardware time counters, or by firmware delay loops. In interrupt coalescing, the NIC “saves up” or stores a group of pending interrupts, and then delivers them all at the same time to the computer system or other node intended to receive them. Thus, the overhead required in processing each interrupt individually is avoided.
While the interrupt coalescing techniques described above are useful in reducing overhead or consumption of a computer system processor, such techniques result in increased per packet latency. Moreover, such techniques are not typically well suited for use with smaller packets, particularly packets such as locking packets, that carry important interrupt messages. A locking packet generally directs a computer system to receive data that follows the locking packet without delay. Thus, it would be desirable to interrupt the system processor immediately upon receiving packets of this type, and not subject such packets to the delays associated with interrupt coalescing techniques of the type described above.